The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure.
In highly miniaturized semiconductor devices of these days, so-called multilayer interconnection structure is used for connecting a vast number of semiconductor elements formed on a substrate electrically. In a multilayer interconnection structure, a large number of interlayer insulation films embedded with interconnection patterns are laminated, wherein an interconnection pattern of one layer is connected to an interconnection pattern of an adjacent layer or to a diffusion region in a substrate by way of a contact hole formed in the interlayer insulation film.
Patent Reference 1
Japanese Laid-Open Patent Application 2005-286058
Patent Reference 2
Japanese Laid-Open Patent Application 2005-191540
Patent Reference 3
Japanese Laid-Open Patent Application 2004-296644
Patent Reference 4
Japanese Laid-Open Patent Application 2004-273523
Patent Reference 5
Japanese Laid-Open Patent Application 2003-197623
Patent Reference 6
Japanese Laid-Open Patent Application 2001-298084